A Novel Dynamic Power Cutoff Technology (DPCT) for Active Leakage Reduction in Deep Submicron VLSI CMOS Circuits

A Novel Dynamic Power Cutoff Technology (DPCT) for Active Leakage Reduction in Deep Submicron VLSI CMOS Circuits

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Due to the exponential increase of subthreshold and gate leakage currents with technology scaling, leakage power is increasingly significant in CMOS circuits as the technology scales down. The leakage power is as much as 50% of the total power in the 90nm technology and is becoming dominant in more advanced CMOS technologies with smaller feature sizes. Also, the leakage in active mode is significantly larger due to the higher die temperature in active mode. Although many leakage reduction techniques have been proposed, most of them can only reduce the circuit leakage power in standby mode.It has been reported that reverse body biasing lowers integrated circuit leakage by three orders of magnitude in a 0.35I¼m technology [38]. ... Hence, this technique is only suitable for ultra-low voltage (0.6V and below) circuits in bulk CMOS.


Title:A Novel Dynamic Power Cutoff Technology (DPCT) for Active Leakage Reduction in Deep Submicron VLSI CMOS Circuits
Author: Baozhen Yu
Publisher:ProQuest - 2007
ISBN-13:

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